Flash manufacturers include foundries, e.g. TSMC and Globalfoundries. Flash technology developers such as Silicon Storage Technology, Inc. (SST) provide embedded NVM technology to foundries inter alia.
US2010027335A describes wear level optimization which takes into consideration both the number of times a page was erased, and the time elapsed from last erase performed for a specific page.
A Freescale Semiconductor, Inc. document by K. Keating et al, entitled “Programming and Erasing FLASH Memory on the MC68HC908AS60” and referenced AN1827 describes Programming and Erasing FLASH Memory on MC68HC908AS60 devices and teaches inter alia that “Program disturb is avoided by using an iterative program and margin read technique known as the smart programming algorithm” and that “the internal charge pump is required for program, margin read, and erase operations of the flash”.
Applications including a processor and memories (e.g. SoC—systems on chip) conventionally provide a configurable and programmable interface control unit, typically implemented in hardware and allowing the processor to use the memory e.g. to translate logical operations such as fetch, read, write, and erase/program (for nonvolatile memory) into electrical signaling to the memory. Any parameters used for managing flash memory are, themselves, typically stored in nonvolatile memory.
The disclosures of all publications and patent documents mentioned in the specification, and of the publications and patent documents cited therein directly or indirectly, are hereby incorporated by reference. Materiality of such publications and patent documents to patentability is not conceded.